CMOS manufacturing processes

10 µm 3 µm 1.5 µm 1 µm 800 nm (0.80 µm) 600 nm (0.60 µm) 350 nm (0.35 µm) 250 nm (0.25 µm) 180 nm (0.18 µm) 130 nm (0.13 µm) 90 nm 65 nm 45 nm 32 nm (Double Patterning) 22 nm (End of Planar Bulk CMOS) 16 nm (Transition to Nanoelectronics) 11 nm (Nanoelectronics)

The 90 nanometer (90 nm) process refers to the level of CMOS process technology that was reached in the 2002-2003 timeframe, by most leading semiconductor companies, like Intel, AMD, Infineon, Texas Instruments, IBM, and TSMC.

The origin of the 90 nm value is historical, as it reflects a trend of 70% scaling every 2-3 years. The naming is formally determined by the International Technology Roadmap for Semiconductors (ITRS), hosted by Sematech.

The 193 nm wavelength was introduced by many (but not all) companies for lithography of critical layers mainly during the 90 nm node. Yield issues associated with this transition (due to the use of new photoresists) were reflected in the high costs associated with this transition.

Even more significantly, the 300 mm wafer size became mainstream at the 90 nm node. The previous wafer size was 200 mm diameter.

As of 2008, 65 nm technology is largely replacing 90 nm technology in leading-edge chip products. However, some products, notably chipsets, have moved from older 130 nm technology to the 90 nm process.

Example: Elpida 90 nm DDR2 SDRAM process

• Use of 300 mm wafer size
• Use of KrF (248 nm) lithography with optical proximity correction
• 512 Mb
• 1.8 V operation
• Derivative of earlier 110 nm and 100 nm processes

Sources: Elpida's presentation at Via Technology Forum 2005 and Elpida 2005 Annual Report

See also

• Photolithography

References

External links

• PC World Review
• Review ITworld
• AMD
• Fujitsu
• Intel
• August, 2002 release by Intel